1. Field of the Invention
The present invention relates to semiconductor fuses, and more particularly to, a shift register for sequential fuse latch operation.
2. Discussion of Related Art
Semiconductor circuits, like processors, microcontrollers, or memories, use fuse elements that allow chips to be configured individually. Parameters such as internal timings, supply voltage level, chip identification number and repair information can be adjusted on a per chip basis. For example, repair information can be used in memory circuits like DRAMs to control the way spare elements are used to repair defects. A typical 64 Mb DAM circuit comprises thousands of fuse elements. As the memory capacity of these semiconductor circuits increase, the number of fuses also increases.
The fuses can be evaluated by a fuse latch circuit, which translates an analog resistance value of a fuse link into a digital value (xe2x80x9chighxe2x80x9d or xe2x80x9clowxe2x80x9d). In addition, the fuse latch stores the digital value. FIG. 1 shows a fuse latch 100 in the lower right corner. For fuse evaluation, the signal 101 is brought low to turn on the PFET 103. This precharge operation causes the internal node 114 to go high. Even after the PFET is turned off again, the latch will keep the high value through the feedback loop (inverter 106).
A precharge operation is needed to initialize the fuse latch ahead of the actual fuse evaluation. The fuse evaluation can be started by bringing the read signal 102 high to turn on the NFET 104. The PFET of the feedback inverter 106 will sink a current through the fuse 105. If the fuse resistance is low, the voltage of the internal node 114 will drop and cause the latch to flip into the opposite state. In the case of a high fuse resistance however, the voltage drop will be small and the latch will not switch its state.
The precharge operation and the read operation cause a current flow. During the precharge operation, current flows from the positive voltage supply 109 through the PFET 103 and the NFET of the feedback inverter 106 to the ground voltage supply 108. The current flow stops after the fuse latch is tripped to the high state of node 114, which turns off the NFET of the feedback inverter 106.
During the read operation, a current flows from the positive power supply through the PFET of the feedback inverter 106, the NFET 104 and the fuse element 105 into the ground power supply 108. If the fuse resistance is low, the latch will trip to the low state of the internal node 114 and the current flow ceases. However, if the fuse resistance is high, the latch can remain in the high state and a constant current can be drawn from the power supply through the path outlined above.
As explained earlier, a single semiconductor chip can comprise several thousand fuse elements and the corresponding fuse latches. To minimize circuit area, those fuse latches typically share control signals (101, 102) and power supply lines (108, 109). Thus, the latches are operated simultaneously. The upper half of FIG. 1 shows a typical configuration of parallel connected fuse latches, the cumulative current of all latches is drawn from the power supply lines. The power supply connections exhibit an internal resistance 112 and 113, which results from the resistance of metal wires, contacts holes, bonding pads, etc. Therefore, a voltage drop occurs across the power supply lines, leading to a reduced positive supply voltage and an increased ground supply voltage whenever the fuse latches draw a current. If the number of fuse latches connected in parallel is high, the voltage drop can be so large that the precharge operation or the read operation is not executed correctly. This can lead to a misreading of the fuse value, which in turn can cause the malfunction of the chip.
Therefore, a need exists for a system and method for a shift register for sequential fuse latch operation.
According to an embodiment of the present invention, a sequential fuse latch device is provided. The sequential fuse latch device (hereinafter xe2x80x9cdevicexe2x80x9d) comprises fuse latches, each fuse latch comprising a data storage element and a fusible link. The device further comprises a shift register comprising pointer latches, wherein each pointer latch is connected to at least one fuse latch, wherein the shift register controls a sequential operation of the plurality of fuse latches.
The operation is a read operation of the fuse latches. The operation is a precharge operation of the fuse latches. The operation is a precharge operation of a first fuse latch and a read operation of a second fuse latch.
Each pointer latch comprises an initialization circuit. The initialization circuit presets a state of the pointer latch.
Each pointer latch controls one of a fuse read operation, a fuse latch precharge operation, and a fuse read operation and a fuse latch precharge operation.
A fuse corresponding to a fuse latch is programmable, and wherein each pointer latch controls a programming operation according to an evaluation of the fuse latch.
Each fuse latch is connected to two corresponding pointer latches, wherein each pointer latch comprises a precharge control signal connected to a first fuse latch and a read operation control signal connected to a second fuse latch.
The device comprises an initialization signal connection to each pointer latch.
The device further comprises a common power supply connected to each fuse, a clock signal connected to each pointer latch, and a shift signals connected in series between each pointer latch.
The pointer latches propagate a value of an initialized pointer latch through the shift register in response to a clock signal.
According to an embodiment of the present invention, a sequential fuse latch device comprises an array of fuse latches, wherein each fuse latch is a data storage element, and a shift register comprising operation inputs to the array of fuse latches, wherein the shift register controls a sequential operation of the fuse latches.
The operation is a read operation of the fuse latches. The operation is a precharge operation of the fuse latches. The operation is a precharge operation of a first fuse latch and a read operation of a second fuse latch.
Each fuse latch device comprises a first transistor connected to a precharge signal and a power supply, a latch connected to a data signal, comprising a second transistor and connected to the first transistor, wherein the first and second transistors precharge the latch, and a third transistor connecting the data signal to a fuse, wherein a read signal and a fuse power up signal control the third transistor and a read operation of the fuse. The device further comprises a fourth transistor connecting the data signal to a power supply. The device comprises transfer gates connected to the data signal, wherein each transfer gate connected to a clock signal, and a second latch, wherein an adjacent sequential fuse latch device is connected to a data shift output of the second latch.
According to an embodiment of the present invention, a method is provided for sequential fuse operation. The method comprises initializing a first pointer latch to a first voltage, initializing a plurality of second pointer latches to a second voltage, and precharging a plurality of fuse latches connected to the plurality of second pointer latches. The method further comprises propagating an initial value of the first pointer latch through each of the plurality of second pointer latches, and activating an operation of each fuse latch as the initial value is propagated.